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2. ASIC gates: This is the number of logic gates that is consumed by the AES core in an ASIC. 3. Best possible throughput: This is the maximum number of data bits that can be processed per second in the best-case scenario. Best case refers to the situation where there is the least amount of penalty delay due to expanding new keys. 4. Worst-case throughput: Worst case here refers to the situation where there is the greatest amount of penalty delay due to expanding new keys. This situation arises when every data block has a unique key. As can be seen from the data in Tables 4.1 and 4.2, the fully pipelined architecture is two orders of magnitude faster (in terms of throughput) under the worstcase scenario of a new key introduced for every data block. Note that the pipelined architecture is penalized for frequent key changes if it cannot ll the pipeline until previous encryptions are complete. This is what accounts for the drastic drop from best-case to worst-case throughput in the standard pipelined architecture.

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3 VLSI routing as a motion planning problem (designing a printed board is a variation of this problem) Assume that after a VLSI chip has been already designed, a need appears to add another few wires With the traditional tools, the whole design must be recalculated from scratch; this is expensive and not always possible Address the task as a motion planning problem The new wires cannot intersect those already on the chip, so the old wires and other electronics on the chip present obstacles to new wires Options may include motion only in one plane or between planes, in which case a wire may jump from plane to plane only in designated points 4 Motion planning amongst moving obstacles The topic can be formulated for either a mobile robot or an arm manipulator.

Investigate the constraints, if any, to be imposed on the velocities and directions of motion of the obstacles (relative to the robot) to make the problem tractable 5 Mutual collision avoidance of two arm manipulators operating in shared space 6 Effect of arm kinematics on workspace accessibility in the presence of obstacles As we learned in s 5 and 6, an interaction between the arm and an obstacle creates shadows, which is effectively a part of workspace that is not accessible to the arm For the same size and shape obstacle, the amount of workspace lost due to this effect depends on the arm kinematics and relative dimensions of its links Investigate this phenomenon 7 Algorithm for coordinating information from different sensors for example, in the context of sensitive skin sensors.

As can be seen from the comparisons section, one of the primary issues with a fully pipelined design is area utilization. Also an issue with this pipelined architecture is the number of block RAMs needed to hold the S-box transformation look-up table. Many modern implementations use the block RAM LUT approach as it is easy to implement and can generate the necessary transformation in a single clock cycle. An arbitrary mapping over GF(28) will require one 8 256 RAM module. A single mapping would not cause an issue, but considering that approximately 320 look-ups need to be performed on every clock, this presents a major issue for FPGA implementations because this memory requirement pushes the limits of even the larger modern FPGAs. Another solution would be to implement the multiplicative inverse using the Extended Euclidean Algorithm as outlined in various technical references. However, the algorithm to compute the inverse of an arbitrary polynomial in GF(2m) has complexity of O(m) and requires 2 m calculations. These steps cannot be placed in parallel for ef cient hardware because each calculation depends on the previous. This type of iterative algorithm may be acceptable for software implementations, but the latency in a hardware implementation (2 m Rounds 160 to 224 clocks) may be unacceptable for applications frequently encrypting small amounts of data. A third approach to implementing the S-box in hardware was proposed by Vincent Rijmen (one of the inventors of Rijndael). The idea is to represent every element of GF(256) as a polynomial of the rst degree with coef cients from GF(16). Denoting the irreducible polynomial as x2 Ax B, the multiplicative