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module setreset( output reg oDat, input iReset, iClk, input iDat1, iDat2); always @(posedge iClk or negedge iReset) if(!iReset) oDat <= 0; else oDat <= iDat1 | iDat2; endmodule

9 8 1

I stopped drawing my portrait of the managing partner, and asked: Which document specifically do you want me to find He stopped talking and stared me down again for what seemed like forever I thought at any moment he would pounce on me, his little Danny DeVito frame scrambling across the desk to rip out my throat or something I took a step back The phone was still sitting on his desk, and I could barely hear a voice calling out to him, wondering where Herb went I think Herb was partly glad I had interrupted him so that he could get back to billing three people at once It s a letter, he answered, as he started walking around his desk to pick up his briefcase As he described the letter, he was already in the process of doing something else entirely.

7 5 6 10

In the code example above, an external reset signal is used to reset the state of the ip- op. This is represented in Figure 2.15. As can be seen in Figure 2.15, a resetable ip- op was used for the asynchronous reset capability, and the logic function (OR gate) was implemented in discrete logic. As an alternative, if we remove the reset but implement the same logic function, our design will be optimized as shown in Figure 2.16. In this implementation, the synthesis tool was able to use the FDS element ( ip- op with a synchronous set and reset) and use the set pin for the OR operation. Thus, by allowing the synthesis tool to choose a ip- op with a synchronous set, we are able to implement this function with zero logic elements.

q1 = 90

q1 = 0

blocks. Each incremental expansion block generates a single word (128/4 32 bits) for the key as described in the NIST speci cation. Each of these blocks is given a pipeline stage. This is shown in Figure 4.11. As mentioned above, each Key-Exp1 block generates a single word (32 bits) of the expanded key. The stages to add pipelining is shown in Figure 4.12. As can be seen in Figure 4.12, the S-box can be implemented as a synchronous 8 256 ROM, and to preserve latency timing accuracy, a pipeline stage must also be added to the R-CON calculation as described in the NIST speci cation. Also, to ensure that the latency timing between the key pipeline and the data propagation pipeline is accurate, the keys must be generated one clock cycle earlier than the round data is completed. This is because the round key is necessary for the add-round-key block that clocks the XOR operation into its nal register. In other words, clock 4 of the key expansion block must be synchronous with clock 3 of the corresponding Round block. This is handled by the initial key addition at the beginning of the key expansion process. This is shown in Figure 4.13. The key data beyond the rst 128 bits begins to expand on the rst clock cycle, while the data pipeline begins on the second clock (a one-clock latency

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+ q1 (b)

Figure 5.24 Revolute prismatic (RP) parallel two-link arm. (a) W -space, with obstacles A and B. Shadows (shaded) result from interaction between the rear end of link l2 with obstacle A and the front end of l2 with obstacle B. (b) C-space images of the corresponding virtual obstacles. Line (S, T ) is the image of the straight line (S, T ) in W -space.

from the initial add-round-key operation). The top-level implementation is shown in the code below for Nk 4.